1. Field of the Invention
The present invention is directed to methods and systems for protecting integrated circuits (xe2x80x9cICsxe2x80x9d) from power-on sequence currents and, more particularly, to methods and systems for providing interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals.
2. Background Art
Circuit boards commonly use multiple power supplies. When the power supplies are powered on at different times, undesired currents tend to flow between the power supplies. These undesired currents are referred to herein as power-on sequence currents. Power-on sequence currents can damage integrated circuits (xe2x80x9cICsxe2x80x9d) on the circuit boards.
For example, core logic may be designed to operate at VDDC/VDDP (1.2V/1.5V/1.8V/2.5V) while an output driver may be required to operate at VDDP/VDDO (1.5V/1.8V/2.5V/3.3V). Voltage level shifting circuits are typically used to interface core signals to the output driver control signals. Voltage level shifting circuits may be designed to operate between two or more power supplies such as VDDO and VDDC. Gate-oxide portions of transistors in these level-shifting circuits may be able to withstand maximum of VDDO-VDDC across the gate-oxide portions.
When these ICs are put into system boards, the different power-supplies may be powered-on at different times. For instance, VDDO may be powered-on before VDDC. This can cause a voltage higher than VDDO-VDDC to appear across the gate-oxide of these transistors during the power-up, potentially damaging the gate-oxide.
Another situation that can cause problems is when I/O buffers require multiple level power supplies, such as 3.3V or 2.5V for example, to interface with other circuits. A number of different I/O buffer circuits may be designed on a chip. In such a design, I/O buffers are selected according to the input signal level or I/O supply voltage level. If the I/O pad voltage is powered up before the core supply voltage is powered up, the core supply voltage may not select a proper I/O buffer circuit. As a result, a higher I/O supply voltage may be inadvertently applied to thinner gate-oxide/shorter gate length I/O circuitry.
Problems similar to those described above can also occur during transients and/or glitches on power supply lines during normal operations.
Methods and systems are needed to protect circuits from over-voltage conditions across IC terminals during power-on sequences, and/or during transients and/or glitches on power supply lines during normal operations.
The present invention is directed to methods and systems for protecting integrated circuits (xe2x80x9cICsxe2x80x9d) from power-on sequence currents. More particularly, the present invention is directed to methods and systems for providing interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals. The present invention is also directed to methods and systems providing interim voltages during transients and/or glitches on power supply lines during normal operations.
In an embodiment, a plurality of power supplies associated with a circuit are monitored. During power-up, if a first power supply is powered-up before a second power supply is powered-up, an interim voltage is provided in place of the second power supply. When the second voltage supply is powered-up, the interim voltage is deactivated.
During the monitoring process, the voltages are compared with one another and/or with one or more thresholds. For example, in an embodiment, voltages at first and second terminals of a circuit are monitored. When the voltage at the first terminal exceeds a first threshold, indicating that a first power supply is powered-on, and a voltage at the second terminal is below a second threshold, indicating that a second power supply is powered off, a voltage from an interim voltage supply is provided to the second terminal until the second power supply is powered-on.
The interim voltage protects the circuit from excessive voltage differences across the terminals during power-on sequences. In an embodiment, the interim voltage also protects the circuit during transients and/or glitches. The interim voltage is deactivated during normal operation so as not to draw excessive current. The invention helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.
The present invention is compatible with digital CMOS process technologies and typically does not require additional masking steps. In an embodiment, no additional power supplies are required for implementing the invention. Circuitry for implementing the invention uses minimal area.